Fabrication of integrated circuitry can comprise forming multiple layers of material, one over the other, and patterning and etching such layers to form various integrated circuit devices. It is highly desirable that precise alignment occur when one layer is formed over another layer and subsequently etched to form a device. Typically, alignment can be maintained between adjacent elevationally displaced layers in a number of different ways. One way is to use alignment marks in so-called scribe areas of the wafer intermediate die areas where active devices are to be formed. The scribe areas can then be inspected either visually or through automated means, and alignment of the layers ascertained.
One alignment regime is referred to as box-in-box alignment because elevationally displaced boxes are formed and examined relative to one another to ascertain whether the layers within which the boxes are formed are aligned. Specifically, a large box might be formed on one layer. A layer overlying the large box will have a layer of photoresist patterned thereover. The patterned layer of photoresist will contain integrated circuitry patterns as well as, over the scribe area and larger box, a smaller box which preferably has an inspectible positional relationship relative to the underlying larger box. The smaller box is typically formed to be received entirely within the larger box when inspected from a position over the wafer or substrate. When inspected, if the smaller box is offset relative to the larger box, one can ascertain that an undesirable misalignment has occurred with the photoresist which can be subsequently cured by removing the photoresist and reapplying it.
One problem associated with alignment pattern usage is that the metrology equipment which is utilized to inspect and ascertain alignment (or for that matter a human inspector) can sometimes have the job complicated by the fact that one or more of the alignment marks can have portions which are undesirably missing or removed. For example, it is often desirable to planarize certain layers of a wafer during processing. Oxide insulative materials such as borophosphosilicate glass (BPSG) are often mechanically abraded as by chemical mechanical polishing to ensure provision of a planar surface for a next-applied layer. Yet, such chemical mechanical polishing can, and often does affect the integrity of one or more of the formed alignment patterns. For example, in the context of box-in-box alignment patterns, portions of the abrupt corners of the boxes can be worn away by the chemical mechanical polishing. Subsequent inspection is made much more difficult because the complete alignment picture is not easily ascertained from the incomplete alignment patterns.
This invention arose out of concerns associated with providing improved methods of ascertaining alignment during semiconductor wafer processing.